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16-bit 500 ksps pulsar tm unipolar adc with reference ad7652 features throughput: 500 ksps 16-bit resolution analog input voltage range: 0 v to 2.5 v n o pipeline delay parallel and serial 5 v/3 v interface spi ? /qspi tm /microwire tm /dsp compatible single 5 v supply operation power dissipation 65 mw typ, 130 w @ 1 ksps without ref 80 mw typ with ref 48-lead lqfp and 48-lead lfcsp packages pin-to-pin compatible with pulsar adcs applications data acquisition instrumentation digital signal processing spectrum analysis medical instruments battery-powered systems process control general description th e ad7652* is a 16-b i t, 500 ks ps, c h a r g e r e dis t r i b u tio n sar a n alog-t o-dig i t a l co n v er t e r t h a t o p era t es f r o m a sin g le 5 v p o we r su p p ly . the p a r t c o n t ains a hig h sp e e d 1 6 - b i t s a m p l i ng a d c , an i n te r n a l c o n v e r s i on cl o c k , i n te r n a l re f e re nc e, e r ror c o rr ecti o n c i r c u i t s , a n d bo th se ri al a n d pa r a ll e l s y s t e m i n t e rf a c e po r t s . th e ad7652 is fa b r ica t ed usin g analog devices hig h p e r f o r m- a n ce , 0.6 micr o n cm os p r o c es s, wi th co r r es p o n d in g l y lo w cos t , a n d is a v a i la b l e in a 48-le ad lqfp a n d a t i n y 48-le ad lfcs p wi t h o p era t io n sp e c if ie d f r o m C40c t o +85c. * p a te nt p e nd ing. functional block diagram 02965-0-001 switched cap dac 16 control logic and calibration circuitry clock ad7652 data[15:0] busy rd cs ser/par ob/2c ognd ovdd dgnd dvdd avdd agnd ref refgnd in ingnd pd reset serial port parallel interface cnvst ref refbufin pdbuf pdref byteswap f i g u r e 1. f u nc t i onal block d i ag r a m table 1. pulsar selection t y p e / k s p s 1 0 0 C 2 5 0 5 0 0 C 5 7 0 800C 1000 pseudo- differential ad7651 ad7660 / ad7661 ad7650 / ad7652 ad7664 / ad7666 ad7653 ad7667 true bipolar ad7663 ad7665 ad7671 true differential ad7675 ad7676 ad7677 18-bit ad7678 ad7679 ad7674 multichannel/ simultaneous ad7654 ad7655 product highlights 1. fa s t t h r o u g hput . th e ad7652 is a 500 ks ps, c h a r g e r e dis t r i b u tio n , 16-b i t sa r a d c w i th i n t e rn al e r r o r co rr ecti o n ci r c ui tr y . 2. int e r n a l r e f e r e n c e . th e ad7652 has a n in t e r n al r e f e r e n c e wi th a typ i cal t e m p era t ur e dr if t o f 7 p p m /c. 3. s i ng l e - supp l y o p e r a t i o n . th e ad7652 o p era t es f r o m a sin g le 5 v s u p p l y . i t s p o w e r dissi p a t io n de cr e a s e s wi t h t h r o ug h p u t . 4. se ri al o r p a r a ll e l i n t e rf a c e . v e rs a t ile p a ral l e l o r 2-wir e s e r i al in t e r f ace a r ra n g em en t is co m p a t i b le wi th bo th 3 v a n d 5 v log i c. rev. 0 in fo rmatio n furn ish e d by an alo g d e v i ces is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any i n fri n gement s of p a t e nt s or ot her ri ght s of t h i r d p a rt i e s t h at may resul t from i t s use. s p ecificatio n s subj ect to ch an g e with o u t n o tice. no licen s e is g r an ted by implicatio n or ot herwi s e under any p a t e nt or p a t e nt ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4700 www.analog.com fax: 781. 326. 8703 ? 2003 analog devices, i n c. all r i ghts r e ser v ed .
ad7652 t a ble of contents s p e c if ica t io n t i min s p e c if ica t io n 5 a o l u t e m a im u m r a t i n 7 p i n c o nf iura t io n a n f u n c t i o n d e c r i p t io n d e f i ni t i o n o f s p e c if ica t io n 11 t y p i cal p e r f o r ma n c e c h a r ac t e r i t ic 12 cir c ui t i n fo r m a t io n 15 c o n er t e r o p era t io n 15 t y p i cal c o nn e c t i o n dia ra m 17 p o w e r di i p a t io n e r u thr o u h p u t 1 c o n erio n c o n t r o l 1 di i t a l i n t e r f ace 20 p a ral l e l i n t e r f ace 20 s e r i al i n t e r f ace 20 m a t er s e r i al i n t e r f ace 21 s l a e s e r i al i n t e r f ace 22 micr o p r o ce o r i n t e r f acin 2 a p plica t io n h i n t 25 b i p o la r a n i er i n p u t r a n e 25 l a yo u t 25 e al ua tin th e ad7652 p e r f o r ma n c e 25 o u t l in e dim e n io n 26 or er i n g u i e 26 reision history re iio n 0 i n i t ia l e rio n rev. 0 | page 2 of 28
ad7652 specifications tale 2 0c to 5c add ddd 5 odd 27 to 525 unle otherwie note p a r a m e t e r c o n i t i o n m i n t y p m a u n i t r e s o l u t i o n 1 6 b i t analog input oltae rane in ingnd 0 ref operatin input oltae in 0 1 ingnd 0 1 0 5 analo input cmrr f in 10 kh 65 b input current 500 ksps throuhput 61 a input impeance 1 throughput speed complete cycle 2 throuhput rate 0 500 ksps dc accuracy interal linearity error 6 6 lsb 2 no m i in co e 15 bit differential linearity error 2 lsb tranition noie 07 lsb unipolar ero error t min to t max 5 l s b unipolar ero error temperature drift 0 2 p p m c full-scale error t min to t max ref 25 012 of fsr full-scale error temperature drift 05 ppmc power supply senitiity add 5 5 2 lsb ac accuracy s i n a l - t o - n o i e f in 100 kh 6 b spuriou free dynamic rane f in 100 kh b t o tal harmonic ditortion f in 5 kh b f in 100 kh 6 b sinal-to-noie ditortion f in 100 kh 6 b 60 b input f in 100 kh 0 b b input banw ith 12 mh sampling dynamics aperture delay 2 n aperture i tter 5 p rm tranient repone full-scale step 750 n r e f e r e n c e internal reference oltae ref 25c 2 25 252 internal reference temperature drift 0c to 5c 7 ppm c line reulation add 5 5 2 p p m turn-on settlin time c ref 10 f 5 m temperature pin oltae output 25c 00 m temperature senitiity 1 mc output reitance k eternal reference oltae rane 2 25 add 15 eternal reference current drain 500 ksps throuhput 110 a re 0 pae of 2
ad7652 p a r a m e t e r c o n i t i o n m i n t y p m a u n i t digital inputs loic leel il 0 0 ih 20 ddd 0 i il 1 1 a i ih 1 1 a digital outputs data format 5 pipeline delay 6 ol i sin 16 ma 0 oh i sou r ce 500 a odd 06 poer supplies specifie performance a d d 7 5 5 5 2 5 d d d 7 5 5 5 2 5 o d d 2 7 525 7 operatin current 500 ksps throuhput add ith reference an buffer 122 ma add reference an buffer alone ma ddd 10 m a odd 10 1 0 2 a power diipation without ref 10 500 ksps throuhput 65 75 m 1 ksps throuhput 10 power diipation with ref 10 500 ksps throuhput 0 0 m temperature range 11 specifie performance t min to t max 0 5 c 1 s e e ect ion a n alo in put 2 ls b me an l e a t i nif icant it ith the 0 to 25 input rane 1 lsb i 15 s e e ect ion th ee pecificat ion o n o t in clue t h e error con t r iut ion from t h e et e rn al referen ce d e f i n i t i on of specificat ion all peci f i c a t i o n i n b a r e referre t o a full- ca l e i n put fs te t e wi t h a n i n put i n a l a t 05 b elow full- ca l e un le otherwi e p ecif ie 5 pa ra llel or seri a l 16- bi t 6 c o ner i on re u l t are aail al e imme iatel y af ter compl e te coner i on 7 the ma h oul e the minimum of 525 an ddd 0 ith re f p dre f an p d buf are lo wi thout ref pdref an pdbuf are high i t h pd r e f pd buf lo a n pd high 10 tet e i n pa ra llel r e a i n moe 11 c o n ul t f a cto ry f o r e te n e t e mperat ure ran e re 0 pae of 2
ad7652 timing specifications table 3. ?40c to +85c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted parameter symbol m i n t y p m a x u n i t refer to figure 26 and figure 27 convert pulsewid t h t 1 1 0 n s time between conversions t 2 2 s cnvst low to busy high delay t 3 3 5 n s busy high all modes except master serial read after convert t 4 1 . 2 5 s aperture delay t 5 2 n s end of conversion to busy low delay t 6 1 0 n s conversion time t 7 1 . 2 5 s acquisition time t 8 7 5 0 n s reset pulsewid t h t 9 1 0 n s refer to figure 28, figure 29, and ( p arallel interface m o d e s) cnvst low to data valid delay t 10 1 . 2 5 s data valid to busy low delay t 11 1 2 n s bus access request to dat a valid t 12 4 5 n s bus relinquish t ime t 13 5 1 5 n s refer to figure 32 and figure 33 (mas t er serial interface modes ) 1 cs low to sync valid delay t 14 1 0 n s cs low to internal sclk valid delay 1 t 15 1 0 n s cs low to sdout delay t 16 1 0 n s cnvst low to sync delay t 17 5 2 5 n s sync asserted to sclk first edge delay t 18 3 n s internal sclk period 2 t 19 2 5 4 0 n s internal sclk high 2 t 20 1 2 n s internal sclk low 2 t 21 7 n s sdout valid setup time 2 t 22 4 n s sdout valid hold t ime 2 t 23 2 n s sclk last edge to sync delay 2 t 24 3 n s cs high to sync hi-z t 25 1 0 n s cs high to internal sclk hi-z t 26 1 0 n s cs high to sdout hi-z t 27 1 0 n s busy high in master serial read after convert 2 t 28 see table 4 cnvst low to sync asserted delay t 29 1 . 2 5 s sync deasserted to busy low delay t 30 2 5 n s r e f e r t o a n d ( s l a ve serial interface modes ) 1 external sclk setup time t 31 5 n s external sclk active edge to sdout delay t 32 3 1 8 n s sdin setup time t 33 5 n s sdin hold time t 34 5 n s external sclk period t 35 2 5 n s external sclk high t 36 1 0 n s external sclk low t 37 1 0 n s f i g u r e 3 0 f i g u r e 3 4 f i g u r e 3 5 1 in s e rial interf ace mod e s , the sync , sc lk, an d sdout timings are d e f i ned with a maximum l o ad c l of 10 pf; otherwis e, the l o ad is 60 pf maximum. 2 in serial mast er read durin g con v ert mode. see ta ble 4 for serial mast e r re ad aft e r con v ert mode. rev. 0 | page 5 of 28
ad7652 tale serial clock timin in mater rea after conert d i s c l 1 0 0 1 1 d i s c l 0 s y m o l 0 1 0 1 u n i t sync to scl firt ee delay minimum t 1 1 7 1 7 1 7 n internal scl perio minimum t 1 2 5 5 0 1 0 0 2 0 0 n internal scl perio maimum t 1 0 7 0 1 0 2 0 n internal scl high minimum t 20 1 2 2 2 5 0 1 0 0 n internal scl lo minimum t 21 7 2 1 n sdout ali setup time minimum t 22 1 1 1 n sdout ali hol time minimum t 2 2 0 0 n scl lat ee to sync delay minimum t 2 5 5 1 0 2 0 n busy high ith maimum t 2 2 2 5 5 5 7 5 re 0 pae 6 of 2
ad7652 rev. 0 | page 7 of 28 absolute maximum ratings table 5. ad7652 stress ratings 1 in 2 , temp 2 , ref, refbufin, ingnd, refgnd to agnd avdd + 0.3 v to agnd C 0.3 v ground voltage differences agnd, dgnd, ognd 0.3 v supply voltages avdd, dvdd, ovdd C0.3 v to +7 v avdd to dvdd, avdd to ovdd 7 v dvdd to ovdd C0.3 v to +7 v digital inputs C0.3 v to dvdd + 0.3 v pdref, pdbuf 3 20 ma internal power dissipation 4 700 mw internal power dissipation 5 2.5 w junction temperature 150c storage temperature range C65c to +150c lead temperature range (soldering 10 sec) 300c 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the de vice. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 see voltage reference input section. 4 specification is for the device in free air: 48-lead lqfp; ja = 91c/w, jc = 30c/w 5 specification is for the device in free air: 48-lead lfcsp; ja = 26c/w. i oh 500 a 1.6ma i ol to output pin 1.4v c l 60pf* * in serial interface modes,the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise,the load is 60pf maximum. 02964-0-006 figure 2. load circuit for digital interface timing, sdout, sync, sclk outputs c l = 10 pf 0.8v 2v 2v 0.8v 0.8v 2v t delay t delay 02965-0-007 figure 3. voltage reference levels for timing esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ad7652 pin configuration and f unction descriptions 6 5 2 1 0 2 2 27 26 25 1 1 15 16 17 1 1 20 21 22 2 2 1 2 5 6 7 10 11 12 7 6 5 7 2 1 0 pin 1 identifier top ie not to scale agnd cnst pd reset cs rd dgnd agnd add nc bytesap ob2c nc nc nc no connect ser par d0 d1 busy d15 d1 d1 ad7652 ddiscl1 d12 d e x t i nt d 5 in syn c d6inscl d7 rdcs d in ognd odd d dd dgnd d s dout d s cl d 10syn c d1 1 rde rror p dbuf p dre f re fbufin temp a dd in agnd agnd nc ingnd re fgnd re f 0265-0-002 d2discl0 f i u r e -l e a l fp st - an -l e a lfcsp cp - ta le 6 pi n f u nct i on de c ri pt i o n pin no mnemonic type 1 d e c r i p t i o n 1 6 1 2 agnd p analo power groun pin 2 add p input analo power pin nominally 5 6 7 0 n c n o c o n n e c t byt e sap di parallel m o e selection - 16-it hen lo the lsb i output on d70 an the msb i output on d15 hen high the lsb i output on d15 an the msb i output on d70 5 ob2c di straiht binarybinary two complement hen ob2c i high the iital output i traiht inary when lo the msb i inerte reultin in a two complement output from it internal hift reiter serpar di serialparallel selection input hen lo the para llel port i electe when high the erial interface mo e i electe an ome it of the dat a u are ue a a erial port 10 d01 do bit 0 an bit 1 of the parallel po rt data output bu hen ser par i high thee output are in hih impeance 11 12 d2or discl01 dio hen serpar i lo thee output are u e a bit 2 an bit of the parallel port ata output u hen serpar i high extint i lo an rdcsdin i lo eria l mater rea after conert thee input part of the erial port are ue to low own if eire the internal erial clock that clock the ata output in other erial mo e thee pin are not ue 1 d o r ext int dio hen serpar i lo thi output i ue a bit of the parallel port ata output u hen serpar i high thi input part of the erial port i ue a a iital elect input for chooin the internal ata clock or an e ternal ata clock ith ext int tie lo the internal clock i electe on the scl output ith ext int et to a loic high output ata i ynchronie to an eternal clock inal connecte to the scl input 1 d 5 o r insync dio hen serpar i lo thi output i ue a bit 5 of the parallel port ata output u hen serpar i high thi input part of the erial port i ue to elect the actie tate of the sync inal it i actie in oth mater an lae mo e hen lo sync i actie high hen high sync i actie lo 1 5 d 6 o r inscl dio hen serpar i lo thi output i ue a bit 6 of the parallel port ata output u hen serpar i high thi input part of the erial port i ue to inert the scl inal it i actie in oth mater an lae mo e re 0 pae of 2
ad7652 pin no. mnemonic type 1 d e s c r i p t i o n 16 d7 or rdc/sdin di/o when ser/par is low, this output is used as bit 7 of the parallel port data output bus. when ser/par is high, this input, part of the serial port, is used as either an ex ternal data input or a read mode selection input depending on the state of ext/int . when ext/int is high, rdc/sdin could be used as a data input to dais y-chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on data with a delay of 16 sclk periods after the initiation of the read seq u ence. when ext/int is low, rdc/sdin is used to select the re ad mode. when rdc/sdin is high, the data is output on sdout during conversion. when rdc/sdin is low, the data can be output on sdout only when the conversion is complete. 17 ognd p input/ output interface digital power ground. 18 ovdd p input/ output interface digital power. nominally at the same supply as the host interface (5 v or 3 v). 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power ground. 2 1 d 8 o r sdout do when ser/par is low, this output is used as bit 8 of the parallel port data output bus. when ser/par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stored in an on -chip register. the ad7652 provides the conversion result, msb first, from its internal shift register. th e data format is determined by the logic level of ob/2c . in serial mode when ext/int is low, sdout is valid on both edges of sclk. in serial mode when ext/int is high, if invsclk is low, sdout is update d on the sclk rising edge and valid on the next falling edge; if invsclk is high, sdout is upda ted on the sclk falling edge and valid on the next rising edge. 2 2 d 9 o r sclk di/o when ser/par is low, this output is used as bit 9 of the parallel port data or sclk output bus. when ser/par is high, this pin, part of the serial port, is used as a serial data clock input or output, depending upon the logic state of the ext / int pin. the active edge where the data sdout is updated depends upon the logic state of the invsclk pin. 2 3 d 1 0 o r sync do when ser/par is low, this output is used as bit 10 of the parallel port data output bus. when ser/par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with th e internal data clock (ext/ i nt = logic low) . when a read sequence is initiated and invsync is low, sy nc is driven high and remains high while the sdout output is valid. when a read sequence is initiated and invs ync is high, sync is driven low and remains low while the sdout output is valid. 2 4 d 1 1 o r rderror do when ser/par is low, this output is us ed as bit 11 of the parallel port data output bus. when ser/par and ext/int are high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, when a data read is started an d not complete when the following conversion is complete, the current data is lo st and rderror is pulsed high. 25C28 d[12:15] do bit 12 to bit 15 of the parallel port data o utput bus. these pins are alwa ys outputs regardless of the state of ser/par . 29 busy do busy output. t r ansitions high when a conversi on is started and remains high until the conversion is complete and the data is latched into the on-chip shift register. the falling edge of busy could be used as a data ready clock signal. 30 dgnd p must be tied to digital ground. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled . 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled . cs is also used to gate the ex ternal clock. 33 reset di reset input. when set to a logic high, this pin resets the ad7652 an d the current conversion, if any, is aborted. if not used, this pin could be tied to dgnd. 34 pd di power-down input. when set to a logic high , power consumption is reduced and conversions are inhibited after the current one is completed. 35 cnvst di start conversion. if cnvst is high when the acquisition phase (t 8 ) is complete, the next falling ed ge on cnvst puts the internal sample/ h old into the hold state and initiates a conversion. the mode is most appropriate if low sampling jitter is d e sired . if cnvst is low when the acquisition phase (t 8 ) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. 37 ref ai/o reference input voltage. on-chip reference output voltage. 38 refgnd ai reference input analog ground. 39 ingnd ai analog input ground. 43 in ai primary analog input with a range of 0 v to 2.5 v. rev. 0 | page 9 of 28
ad7652 pin no mnemonic type 1 d e c r i p t i o n 5 temp ao temperature senor oltae output 6 refbufin aio reference input oltae the re ference output an the reference uffer input 7 pdref di t h i pin allow the choice of internal or ete rnal oltae reference hen lo the on-chip reference i turne on hen high the internal reference i witche off an an eternal reference mut e ue pdbuf di thi pin allow the choice of ufferin an inte rnal or eternal reference wi th the internal uffer hen lo the uffer i electe hen high the uffer i witche off 1 ai an a l o in put aio bi i rect i o n a l an a l o ao an a l o out p ut d i d i i t a l in put d io bi i rect i o n a l d i i t a l d o d i i t a l out p ut p power re 0 pae 10 of 2
ad7652 rev. 0 | page 11 of 28 definitions of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last transition (from 01110 to 01111 in twos complement coding) should occur for an analog voltage 1? lsb below the nominal full scale (2.49994278 v for the 0 v to 2.5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. unipolar zero error the first transition should occur at a level ? lsb above analog ground (19.073 v for the 0 v to 2.5 v range). unipolar zero error is the deviation of the actual transition from that point. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s /( n + d ) by the following formula: enob = ( s /[ n + d ] db C 1.76)/6.02 and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal, and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient response transient response is the time required for the ad7652 to achieve its rated accuracy after a full-scale step function is applied to its input. overvoltage recovery overvoltage recovery is the time required for the adc to recover to full accuracy after an analog input signal 150% of the full-scale value is reduced to 50% of the full-scale value. reference voltage temperature coefficient reference voltage temperature coefficient is the change of internal reference voltage output voltage v over the operating temperature range and normalized by the output voltage at 25c, expressed in ppm/c. the equation follows: 6 1 2 1 2 10 ) C ( ) 25 ( ) ( C ) ( ) / ( = t t c v t v t v c ppm tcv where: v (25 c ) = v at +25c v ( t 2 ) = v at temperature 2 (+85c) v ( t 1 ) = v at temperature 1 (C40c)
ad7652 typical performance characteristics code inl l sb 0 1 2 0 2 1 16 276 6556 152 0265-0-02 f i gur e 5 . int e gr a l no nl i n ea ri t y vs . c o de code in he counts 7ffb 0 20000 60000 40000 80000 140000 120000 8000 8001 8003 8002 02965-0-027 8004 7ffc 7ffd 7ffe 7fff 100000 00 0 0 70 477 112112 111974 25889 10598 f i g u r e 6. his t og r a m of 261,120 convers i ons of a dc input a t the c o de t r a n si ti o n frequency (kh) amplitude ( d b of full scale) 0 180 160 120 140 100 60 80 0 100 150 250 200 02965-0-029 50 40 20 f s = 500ksps f in = 102kh snr = 83.4db thd = 90.9db sfdr = 91.2db s/[n+d] = 82.8db f i gur e 7. fft p l ot code dnl (ls b ) 0 1.0 0.5 0.5 0 1.0 2.0 1.5 16384 32768 65536 49152 02966-0-026 f i g u r e 8. d i f f e r e nt ial nonlinearit y v s . code code in he counts 0 20000 80000 40000 100000 160000 120000 8000 8001 8003 8002 02965-0-028 8004 7ffc 7ffd 7ffe 7fff 0 110 8659 801 10 60000 144958 41624 64967 140000 f i g u r e 9. his t og r a m of 261,120 convers i ons of a dc input a t the c o de c e nt er frequency (kh) s nr, s / [n+d] (db) 1 76 79 82 88 100 02965-0-030 1000 10 85 enob ( b it s) 14.5 12.5 13.0 13.5 14.0 enob snr s/[n+d] f i gur e 10. snr, s/(n+d), and e n ob v s . f r equenc y rev. 0 | page 12 of 28
ad7652 frequency (khz) thd, harmonics (db) 1 120 100 80 90 70 50 100 02966-0-031 1000 10 60 s f dr (db) 140 0 100 20 40 60 80 second harmonic sfdr third harmonic 110 thd 120 f i gur e 11. thd , harmonics, and sfdr v s . f r equenc y input level (db) s nr, s / [n+d] re fe rre d to full s cale (db) 60 82 87 02965-0-032 0 50 40 30 20 1 0 83 84 85 86 snr s/[n+d] f i gur e 12. snr and s/(n+d) vs . input l e v e l (referr e d t o f u l l s c al e) temperature ( c) s nr, s / [n+d] (db) 55 85 89 02965-0-033 125 35 15 25 45 65 86 87 88 enob 58 5 105 14.00 14.50 14.13 14.25 14.38 enob ( b it s) snr s[n+d] f i gur e 13. snr, s/(n+d), and enob vs. t e mp er atur e temperature ( c) thd, harmonics (db) 5 5 120 100 02965-0-034 125 35 15 25 45 65 115 105 second harmonic 58 5 105 third harmonic thd 110 f i g u r e 14. thd and harmonics v s . t e mper at ur e sample rate (sps) 10 02965-0-036 1000000 100 10000 100000 10 1000 100 1000 10000 0.001 1 0.01 op e rating curre nt ( rev. 0 | page 13 of 28
ad7652 temperature (c) vr ef ( v ) 40 2.5000 02965-0-039 02 0 4 0 6 0 2 0 8 0 120 2.4970 100 2.4980 2.4985 2.4990 2.4995 2.4975 f i gur e 17. t y pic a l r e fer e nc e o u tput v o ltage v s . t e mper atur e reference drift (ppm/c) numbe r of units 3 0 0 6 10 8 12 20 16 02965-0-040 2 6 2 2 1 8 1 4 14 1 0 6 2 2 3 0 26 22 18 14 10 6 4 2 18 f i g u r e 18. r e f e r e nc e v o lt ag e t e mper at ur e coef f i cient d i s t ribut i on (100 u n it s ) c l (pf) t 12 de lay (ns ) 0 0 50 02966-0-035 200 50 100 150 10 30 40 20 ovdd= 5v @ 25 c ovdd= 5v @ 85c ovdd= 2.7v @ 25c ovdd= 2.7v @ 85c f i g u r e 19. t y pic a l d e lay v s . l oad capacit a nc e c l rev. 0 | page 14 of 28
ad7652 circuit information s a comp s b in ref refgnd lsb msb 276c ingnd 16c c 2c c c 6556c contr o l logic sitches contr ol bu s y output code 026-0-005 cnst f i u r e 20 a d c simplif ie s c hemat i c i ur e 2 0 th e ad7652 i a e r y fa t lo w p o w e r in le u p p l y p r eci e 16- i t a n alo-t o- i i tal co n er t e r ad c d u r i n t h e ac u ii t io n pha e t h e co mm o n t e r m ina l o f t h e a r ra y ti e t o th e co m p a r a t o r poi ti e i n p u t i co n n ect e t o a g n d ia s a a l l in ep e n en t wi t ch e a r e co nn e c t e t o t h e a n alo in p u t in th u th e ca p a ci t o r a r ra y i u e a a a m p lin ca p a ci t o r a n ac u ir e th e a n alo i n al o n in s i mila rl y th e u mm y ca p a ci t o r ac u ir e th e a n alo i n al o n in gnd th e ad7652 p r o ie th e u er wi th a n o n -c hi p trac kh o l u cce i e a p p r o ima t io n ad c t h a t o e n o t ehi i t a n y p i p e lin e o r la t e n c y makin i t ie a l f o r m u l t i p le m u l t i p lee c h a n n e l ap p l i c at i o n h e n cn s t o e l o a co n erio n pha e i ini t ia t e h en t h e co n erio n pha e e i n s a an s b a r e o p en e th e ca p a ci t o r a r ra y a n u mm y ca p a ci t o r a r e th en i co n n e ct e f r o m t h e in p u t a n co nn e c te to ref g nd th er efo r e t h e if f er en tial o l t a e etw een in a n in gnd ca p t ur e a t th e en o f t h e ac u ii t io n pha e i a p plie t o t h e co m p a r a t o r in p u t ca uin th e co m p a r a t o r t o eco m e un ala n c e b y wi t c h in e a ch e l em en t o f t h e ca p a ci t o r a r ra y e tw e e n refgnd a n ref t h e co m p a r a t o r in p u t a r i e y i na r y w e i h t e o l t a e t ep ref 2 ref ref 6556 th e co n t r o l lo i c t o l e th e e w i t c h e t a r ti n w i th th e ms b t o r i n th e co m p a r a t o r a c k i n to a a l a nc e c o n i t i o n th e ad7652 ca n e o p era t e f r o m a in le 5 u p p l y a n ca n e in t e r f ace t o ei th er 5 o r i i tal lo i c i t i h o u e in ei t h er a -le a lfp o r a -le a lfcs p t h a t a e p ace a n al lo w f l ei le co nf iura t io n a ei t h er a e r i al o r p a ral l e l in t e r - face th e ad7652 i p i n-t o -p in co m p a t i le wi th pu lsar ad c conerter operation th e ad7652 i a u cce i e-a p p r o ima t io n ad c a e o n a c h a r e r e i t r i u tio n d a c f h o w a im p lif i e c h e - ma tic o f th e ad c th e ca p a ci ti e d a c co n i t o f a n a r ra y o f 16 i na r y w e i h t e ca p a ci to r a n a n ai t i o n a l ls b ca p a ci to r th e co m p a r a t o r n e a ti e in p u t i co nn ec t e t o a u mm y ca p a ci t o r o f th e a m e a l u e a th e ca pa ci ti e d a c a r ra y af t e r thi p r o c e i co m p let e th e co n t r o l lo i c e n e ra t e th e ad c o u t p u t co e a n r in th e b u s y o u t p u t l o re 0 pae 15 of 2
ad7652 transfer functions us i n g t h e o b / 2c dig i tal in p u t th e ad2 o f f e rs tw o o u t p u t co din g s st r a ig h t b i na r y a n d tw o s co m p lem e n t th e ls b sie is v ref / whic h is a b o u t 1 v th e ad2 s ideal t r a n sfer cha r ac t e r i st ic is sh o w n i n a n d f i gur e 2 1 f i gur e 21 a d c ideal t r ansfer f u nc tion t a b l e ta ble out p ut codes a nd idea l input volt a g es 1 1 11111 11111 111111 adc code (s tra i ght bina ry ) analo input v ref 1 lsb v ref 1 lsb 1l s b v lsb 1 lsb v re f / 29-- digital output code (hex) description analo g input straight binary twos complement fsr 1 lsb 29992 v ffff 1 f f f 1 fsr 2 lsb 29992 v fffe ffe idscale + 1 lsb 12 v 1 1 idscale 12 v idscale 1 lsb 12992 v fff ffff fsr + 1 lsb v 1 1 fsr v 2 2 1 th i s i s a lso t h e code for overra n g e a n a l og i n put (v in v in n d above v re f v re f nd ) 2 th i s i s a lso t h e code for un derra n g e a n a l og i n put (v in below v in n d ) no tes 1 the confiuration shon is usin the internal reference and internal buffer 2 the ad21 is recoended see driver aplifier choice section optional lo itter a 1 ? ?
ad7652 driver amplifier choice typical connection diagram al th o u g h th e ad7652 is easy t o dr i v e , th e dr i v er a m p l if ier n eeds t o m e et t h e fol l o w in g r e q u ir em en ts: f i gur e 2 2 s h o w s a typ i cal co nn ec tio n dia g ra m f o r th e ad7652. analog input ? ? ?
ad7652 oltae reference input f o r a p p l ica t io n tha t u e m u l t i p le ad7652 i t i m o r e ef f e c t i e t o u e t h e in t e r n al u f f er t o u f f er t h e r e fer e n c e o l t a e th e ad7652 al lo w th e c h o i ce o f ei th er a e r y lo w t e m p era t ur e r i f t i n te r n a l o lt ae re f e re nc e or an e te r n a l 2 5 re f e re nc e c a r e h o u l e t a k e n wi t h t h e o l t a e r e fer e n c e t e m p era t ur e c o e f f i c i e n t wh i c h i r e ctl y a f f e ct th e full - c a l e a c cu ra c y i f th i p a ra m e t e r ma t t er f o r in t a n ce a 15 p p m c t e m p era t ur e co ef f i cien t o f t h e r e fer e n c e cha n e f u l l c ale y 1 ls bc u n lik e ma n y ad c wi th in t e r n al r e f e r e n c e th e in t e r n al r e f e r e n c e o f th e ad7652 p r o ie ece l l en t p e r f o r ma n c e a n ca n e u e in a l m o t a l l a p plica t io n no t e t h a t ref ca n e in cr ea e t o a d d 15 s i n c e th e in p u t ra n e i ef i n e in t e r m o f ref t h i w o u l e e n t ia l l y in cr ea e th e ra n e t o 0 t o wi th a n a d d a o e 5 th e ad70 ca n e e lec t e wi th a r e f e r e n c e o l t a e t o u e t h e in t e r n al r e fer e n c e alo n wi t h t h e in t e r n al u f f er p d ref a n p d b u f h o u l o th e l o thi wil l p r o uce a 1207 o l t a e o n refb ufin whic h a m p l if ie y th e u f f er w i l l re u lt i n a 2 5 re f e re nc e on t h e r e f pi n th e temp p i n whic h m e a ur e th e t e m p era t ur e o f th e ad7652 ca n e u e a h o w n i n th e o u t p u t o f temp p i n i a p pl i e to one of t h e i n put of t h e an a l o w itch e ad g77 a n t h e ad c i t e lf i u e t o m e a ur e i t o w n t e m p era t ur e thi co nf iura t io n i e r y u ef u l fo r im p r o in t h e ca li r a t io n acc u rac y o er t h e t e m p era t ur e ra n e th e o u t p u t im p e a n c e o f refb ufin i 11 k minim um w h en t h e in t e r n a l r e f e r e n c e i ena le i t i u ef u l t o eco u p le refb ufin wi th a 100 nf cera mic ca p a ci t o r th u th e 100 nf ca p a ci t o r p r o ie a n r c f i l t er fo r n o i e r e u c t io n f i ur e 2 f i gur e 24. t e mp er atur e s e nsor c o nnec t ion d i agr a m t o us e a n et e r n al r e fer e n c e alo n g wi t h t h e in t e r n al b u f f er , p d ref s h o u ld be hi h a n d p d b u f s h o u ld be l o w . this p o we r s d o w n t h e i n te r n a l re f e re nc e and a l l o w s t h e 2 . 5 v r e f e r e n c e t o be a p p l ied t o refb ufin. ad779 ad8021 c c 02965-0-024 a nalo inpu t (unipolar) ad7652 in t emper a t u r e sen so r temp t o u s e an e te r n a l re f e re nc e d i re c t ly on r e f pi n , pdr e f and p d b u f s h o u ld bo t h be hi h. pdr e f and pdb u f resp e c t i vely p o we r down t h e in te r n a l re f e re nc e and t h e i n te r n a l re f e re nc e bu f f e r . n o te t h a t t h e pdr e f a n d pd b u f in p u t c u r r en t sh o u ld n e v e r ece e d 20 ma. this co u l d e v en t u al l y o c c u r w h en in p u t v o l t a g e is a b o v e a v d d (fo r in s t a n ce a t p o w e r u p ). i n this cas e , a 100 s e r i es r e sis t o r is re c o m m e n d e d. power supply th e ad7652 us es thr e e p o w e r s u p p l y p i n s a n a n alog 5 v s u p p l y a v dd , a dig i t a l 5 v co r e su p p ly d v dd , a n d a dig i t a l in p u t/o u t p u t in t e r f ace su p p ly o v dd . o v dd a l lo ws dir e c t in t e r f ace wi th a n y log i c betw een 2.7 v a n d d v d d + 0.3 v . t o r e d u ce t h e s u p p lies n e e d e d , t h e dig i t a l co r e (d vd d) ca n b e su p p l i e d t h rou g h a s i m p l e rc f i l t e r f r om t h e ana l o g su p p ly , as s h o w n i n . th e ad7652 is in dep e n d en t o f p o w e r s u p p l y s e q u en cin g o n ce o v d d do es n o t ece e d d v d d b y m o r e tha n 0.3 v , a n d is th us f r ee o f s u p p l y v o l t a g e in d u ced la t c h-u p . th e in t e r n al r e fer e n c e is t e m p era t ur e co m p en s a t e d t o 2.5 v 20 mv . th e r e fer e n c e is t r imm e d t o p r o v ide a ty p i ca l dr if t o f 7 . this ty p i ca l dr if t cha r ac t e r i st ic is sh o w n i n . f o r im p r o v ed dr if t p e r f o r ma n c e , a n et e r n al r e f e r e n c e s u c h as th e ad780 ca n be us ed . p p m / c f i gur e 1 7 f i gur e 2 2 th e ad7652 v o l t a g e r e f e r e n c e in p u t ref has a d y na mic in p u t im p e da n c e i t s h o u ld t h er efo r e b e dr i v en b y a lo w im p e da n c e s o ur ce wi t h ef f i cien t de co u p lin g b e tw e e n t h e ref a n d ref nd i n put s . t h i s d e c o upl i ng d e p e nd s on t h e choi c e of t h e vo lt age r e f e r e n c e b u t us ual l y co n s is ts o f a lo w es r ca p a ci t o r co nn ec t e d to ref a n d ref nd wi t h minim u m p a rasi t i c in d u c t a n ce. a 10 f (5r , 1206 sie) cera mic c h i p ca p a ci t o r (o r 47 f ta n t a- l u m ca p a ci t o r) is a p p r o p r i a t e w h en usin g ei t h er t h e in t e r n al r e fer e n c e o r o n e o f t h es e r e co mm en de d r e fer e n c e v o l t a g es ? ? ?
ad7652 poer dissipation ersus throughput th e cn s t trace h o u l e h ie le wi th r o u n a n a lo w al u e e r i al r e i t o r i e 50 ter m ina t io n h o u l e ae clo e t o t h e o u t p u t o f t h e co m p o n en t t h a t r i e t h i lin e o p era t in c u r r en t a r e e r y lo w u r i n t h e ac u ii t io n pha e al lo win i n if ica n t p o w e r a in w h en t h e co n erio n ra t e i r e u ce e e th e ad7652 a u t o ma tical l y r e u ce i t p o w e r co n um p t io n a t t h e en o f e a ch co n erio n pha e thi ma k e t h e p a r t ie a l fo r e r y lo w p o w e r a t t er y a p plica t io n th e i i t a l in t e r f ace a n t h e r e fer e n c e r e ma in ac t i e e en u r i n t h e ac u ii t io n pha e t o r e u ce o p era t in i i t a l u p p ly c u r r en t e en f u r t h e r i i tal in p u t n ee t o e r i en c l o e t o th e p o w e r u p p l y ra il i e d d d o r d g nd a n o d d h o u l n o t ecee d d d y m o r e tha n 0 f i ur e 2 5 f i gur e 2 5 . p o w e r di ssi pa ti o n vs . s a m p l i n g r a t e f o r a p plica t io n s w h er e s n r is cr i t ica l , t h e cnv s t sig n al s h o u ld ha ve ver y lo w i t t er . this ma y b e achie v e d b y usin g a de dica te d oscilla t o r f o r cnv s t ge ne r a t i on , or to cl o c k cnv s t wi t h a hig h f r eq uen c y , lo w i t t er c l o c k, as s h o w n i n . f i gur e 2 2 bu s y mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 a c q uire conver t a cq uire conver t 02964-0-011 cnvst sample rate (sps) 10 02965-0-037 1000000 100 10000 100000 1000 10000 100 1000 100000 10 pow e r dissipation ( conversion control f i gur e 2 6 f i gur e 26. basic con v ersion t i ming t 9 t 8 reset data busy 02964-0-011 cnvst s h o w s th e d e ta iled ti m i n g d i a g ra m s o f th e co n v e r si o n p r o c es s. th e ad7652 is co n t r o l l ed b y th e cnv s t sig n al , whic h ini t ia t e s co n v ersio n . on ce ini t ia t e d , i t ca nn o t b e r e st a r t e d o r a b o r t e d , e v en b y t h e p o w e r - do wn in p u t p d , un t i l t h e co n v ersio n is co m p let e . cnv s t o p era t es in dep e n d en t l y o f cs and rd . f i g u r e 27. r e se t timing c o n v ersio n s ca n be a u t o ma tical l y ini t ia t e d wi th th e ad7652. i f cnv s t is h e ld l o w wh en b u s y is l o w , th e ad7652 co n t r o ls t h e acq u isi t io n phas e a n d a u t o ma t i ca l l y ini t ia t e s a n e w co n v ersio n . by k e ep in g cnv s t l o w , th e ad7652 k e eps th e co n v ersio n p r o c ess r u nnin g b y i t s e lf. i t sh o u ld b e n o te d t h a t t h e a n alog in p u t m u s t be s e t t led wh en b u s y g o es l o w . als o , a t po w e r - u p , cnv s t shou l d b e brou g h t lo w onc e to i n it i a te t h e co n v ersio n p r o c es s. i n this m o de , th e ad7652 ca n r u n s l ig h t l y fas t er tha n th e gua r a n t eed 500 ks ps. t 1 t 3 t 4 t 11 bu s y da t a bu s cs = rd = 0 t 10 previous conversion d a t a new d a t a 02964-0-012 cnvst al th o u gh cnv s t i s a d i gi tal s i gn al , i t s h o u l d be d e s i gn ed w i th s p eci a l ca r e w i th fa s t , c l ea n ed g e s , a n d l e v e l s w i th m i n i m u m ove r sho o t and u n d e r s ho ot or r i ng i n g . f i g u r e 28. m a s t er p a r a llel d a t a timing f o r r e ading (cont i nuous r e ad) rev. 0 page 19 of 28
ad7652 current conersion busy da t a bus t 12 t 1 026-0-01 rd cs digital interface th e ad7652 has a v e rs a t ile dig i tal in t e r f ace; i t ca n be in t e r f aced wi t h t h e h o s t sys t em b y usin g ei t h er a s e r i al o r a p a ral l e l i n t e rf a c e . t h e se ri al i n t e rf a c e i s m u l t i p l e x e d o n th e pa r a ll e l d a ta b u s. th e ad7652 dig i tal in t e r f ace als o acco mm o d a t es bo th 3 v and 5 v l o g i c b y s i m p ly c o nne c t i ng t h e o v dd su p p ly p i n of t h e ad7652 t o th e h o s t sys t em in t e r f ace dig i tal s u p p l y . f i nal l y , b y usin g th e o b / 2c in p u t p i n, bo th tw os co m p lem e n t o r s t ra ig h t b i na r y co din g ca n b e us e d . th e tw o sig n als, cs and rd , c o n t r o l t h e i n t e r f a c e . cs and rd ha v e a simi la r ef fe c t b e ca us e t h e y a r e o r d t o g e t h er in t e r n al l y . w h en a t le as t o n e o f t h es e sig n als is hi gh, t h e in t e r f ace o u t p u t s a r e in hig h im p e da n c e . u s ua l l y cs al lo ws th e s e le c t io n o f eac h ad7652 in m u l t icir c u i t a p p l ica t io n s a n d is h e ld l o w in a sin g le ad7652 desig n . rd is g e n e ral l y us ed t o ena b le th e c o n v e r s i on re su lt on t h e d a t a bu s . parallel interf ace th e ad7652 is co nf igur ed t o us e th e p a ral l e l in t e r f ace wh en se r / pa r is h e ld l o w . th e da ta ca n be r e ad ei th er a f t e r eac h co n v ersio n , w h ich is d u r i n g t h e n e xt acq u isi t io n phas e , o r d u r i ng t h e f o l l ow i n g c o n v e r s i on , a s show n i n f and , r e s p ecti v e l y . w h e n th e d a ta i s r e a d d u ri n g th e co n v ersio n , h o w e v e r , i t is r e co mm en ded tha t i t is r e ad o n l y d u r i n g th e f i rs t half o f th e co n v ersio n p h as e . this a v o i ds a n y po t e n t i a l f eed th r o ugh be t w ee n v o l t a g e tra n si e n t s o n th e d i gi tal in t e r f ace a n d th e m o s t cr i t ical a n alog co n v ersio n cir c ui tr y . i g u re 2 9 f i g u r e 29. slave p a r a llel d a t a timing f o r r e ading ( r ead a f ter conver t ) f i gur e 3 0 f i g u r e 30. slave p a r a llel d a t a timing f o r r e ading ( r ead during conver t ) previous conversion t 1 t 3 t 12 t 13 t 4 bus y da t a bus 02964-0-014 cnvst, rd cs = 0 th e by tesw ap p i n al lo ws a g l ue les s in t e r f ace t o a n 8-b i t b u s. a s s h o w n i n , th e ls b b y t e is o u t p u t o n d[7:0] a n d th e ms b is o u t p u t o n d[15:8] wh en by tesw ap is l o w . w h en by tesw ap is hi gh, th e ls b a n d ms b b y t e s a r e swa p p e d a n d th e ls b is o u t p u t o n d[15:8] a n d th e ms b is o u t p u t o n d[7:0]. by co nn e c t i n g by tesw ap to a n addr ess lin e , t h e 16-b i t da t a ca n be r e ad in tw o b y t e s o n ei th er d[15:8] o r d[7:0]. f i gur e 3 1 f i g u r e 31. 8-bit p a r a llel inter f ac e cs rd byteswap pins d[15:8] pins d[7:0] hi- hi- high byte lo w byte lo w byte high byte hi- hi- t 12 t 12 t 13 02965-0-025 serial interface th e ad7652 is co nf igur ed t o us e th e s e r i al in t e r f ace wh en se r / pa r is h e ld hi gh. th e ad7652 o u t p u t s 16 b i ts o f da ta , ms b f i rst, o n t h e s d o u t p i n. this da t a is sy n c hr o n ize d wi t h t h e 16 clo c k p u ls es p r o v ide d o n t h e sclk p i n. th e o u t p u t da t a i s v a li d o n bo th th e ri si n g a n d falli n g ed g e s o f th e d a ta c l oc k . rev. 0 page 20 of 28
ad7652 u s ual l y , beca us e th e ad7652 is us ed wi th a fas t thr o ug h p u t , m a s t er re ad d u r i n g c o n v ersio n is t h e m o s t r e co mm en de d s e r i a l m o de. i n t h is m o de m o de, t h e s e r i a l clo c k a n d da t a to g g l e at ap p r o p r i at e i n s t a n t s , m i n i m i z i n g p o t e nt i a l f e e d t h r o u g h b e tw e e n dig i t a l ac t i vi ty a n d cr i t ica l co n v ersio n de cisio n s. master serial interface internal c l ock th e ad7652 is co nf igur ed t o g e n e ra t e a n d p r o v ide th e s e r i al d a ta c l oc k sc l k wh e n th e e t / int p i n is h e ld l o w . th e ad7652 als o g e n e ra t e s a s y n c sig n al t o in dica t e t o th e h o s t w h en t h e s e r i al da t a is valid . th e s e r i al clo c k sclk a n d t h e s y n c sig n a l ca n b e in v e r t e d if desir e d . d e p e n d in g o n t h e rd c/s d in in p u t, th e da ta ca n be r e ad a f t e r eac h co n v ersio n o r d u r i n g th e f o l l o w in g co n v ersio n . f a n d s h o w th e d e ta iled ti m i n g d i a g ra m s o f th e s e t w o m o d e s. i gur e 3 2 f i gur e 32. master s e rial d a ta t i mi ng for r e ading (r ead a f ter con v er t) f i gur e 3 3 f i gur e 33. master s e rial d a ta t i ming for read ing (r ead p r ev ious con v ersion during con v er t i n r e a d a f te r c o n v e r s i on mo d e , it shou l d b e note d t h a t u n l i ke in o t h e r m o des, th e b u s y sig n al r e t u r n s l o w a f t e r th e 16 da ta b i ts a r e p u ls e d o u t a n d n o t a t t h e en d o f t h e co n v ersio n phas e , w h ich r e su l t s in a lo n g er b u s y wid t h. t 3 bu s y sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 12 3 1 4 1 5 1 6 d15 d14 d2 d1 d0 rdc/sdin 0 invsclk invsync 0 t 25 t 30 02964-0-015 cnvst cs, rd et/int 0 et/int 0 rdc/sdin 1 invsclk invsync 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d15 d14 d2 d1 d0 12 3 1 4 1 5 1 6 t 18 bu s y sync sclk sdout 02964-0-016 cnvst cs, rd rev. 0 page 21 of 28
ad7652 slave serial interface external c l ock th e ad2 is co nf igur ed t o accep t a n ext e r n al l y s u p p lied se ri al d a ta c l oc k o n th e sc l p i n wh e n th e e t / int pi n i s hel d h i h i n th i s m o d e sev e ral m e th od s ca n be used t o r e a d th e da t a th e ext e r n al s e r i al clo c k is ga t e d b y cs h e n cs and rd a r e bo th l o th e d a ta ca n be re a d af te r e a ch c o n v e r s i on or d u r i n g t h e fol l o w in g co n v ersio n th e ext e r n al clo c k ca n b e e i t h e r a c o n t i n u o u s or a d i s c on t i n u ou s cl o c k a d i s c on t i n u ou s c l o c k ca n be ei th er n o r m al l y hi h o r n o r m al l y l o wh en i n a c ti v e f a n d f s h o w th e d e ta iled ti m i n g dia g ra m s o f t h es e m e t h o d s i gur e f i g u r e slave s e rial d a t a timing f o r r e ading (r ead a f ter conver t ) i gur e f i g u r e slave s e rial d a t a timing f o r r e adin g (r ead p r ev ious con v ersion during con v er t) h ile th e ad2 is p e r f o r min g a b i t decisio n i t is im p o r t a n t t h a t vo lt age t r ans i e n t s b e a v oi d e d on d i g i t a l i n put / output pi ns or deg r ada t io n o f t h e co n v ersio n r e su l t co u l d o c c u r this is p a r t ic u l a r l y im p o r t a n t d u r i n g t h e s e co n d half o f t h e co n v ersio n p h as e beca us e th e ad2 p r o v ides er r o r co r r ec tio n cir c ui tr y t h a t ca n co r r e c t fo r a n im p r o p er b i t de cisio n made d u r i n g t h e f i r s t h a l f of t h e c o n v e r s i on ph a s e f o r t h i s re a s on it i s r e co mm en de d t h a t w h en a n ext e r n al clo c k is b e in g p r o v ide d i t is a dis c o n t i n u o u s clo c k t h a t is t o g g l in g o n ly w h en b u s is l o o r m o r e i m po r t a n tl y th a t i t d o e s n o t tra n si ti o n d u ri n g th e la t t er half o f b u s hi h scl sdout d1 d1 d1 d d1 1 1 1 1 1 1 bu s sdin invscl t t t t 1 t 2 t 1 t 1 1 1 2 1 1 1 1 1 t 29--1 et/int 1 rd rd s dout scl d1 d d1 d1 d1 12 1 1 1 t t t t t 1 t 2 t 1 bu s et/int 1 invscl 29--1 cnvst cs rd rev page 22 of 2
ad7652 eternal dicontinuou clock data rea after con erion eternal c l ock data r e a durin c o ner i on f i ur e 5 h o w th e e ta ile ti m i n i a ra m o f th i m e th o d u r i n a co n erio n w h i l e o t h cs an rd a r e o th l o th e r e u l t o f th e p r eio u co n erio n ca n e r e a th e a ta i h if t e o u t ms b f i r t w i th 16 c l oc k p u le a n i a li o n o th th e r i in a n fal l in e e o f th e c l o c k th e 16 i t m u t e r e a e fo r e t h e c u r r en t co n erio n i co m p let e o t h e r w i e rd err o r i p u l e hi gh a n ca n e u e t o in t e r r u p t th e h o t in t e r f ace t o p r e en t in co m p let e a t a r e ain th er e i n o a iy - cha i n fe a t ur e in t h i m o e a n t h e rd cs d in in p u t h o u l al wa y e tie ei th er hi gh o r l o th o u h t h e ma i m u m t h r o u h p u t ca nn o t e achie e uin t h i m o e i t i t h e m o t r e co mm en e o f t h e e r i al l a e m o e h o w th e e ta ile ti m i n i a ra m o f th i m e th o a f te r a c o n e r i on i c o m p l e te i n i c a te y b u s y re t u r n i n l o t h e co n erio n r e u l t ca n e r e a w h i l e o t h cs an rd a r e lo d a t a i hif t e o u t ms b f i rt wi t h 16 clo c k p u l e a n i ali o n t h e r i in a n fal l in e e o f t h e clo c k f i ur e a m o n th e a a n t a e o f th i m e th o i th e fa ct th a t co n e r i o n p e r f o r ma n c e i n o t e r ae e ca u e t h er e a r e n o o l t a e t r a n - ien t o n t h e i i t a l in t e r f ace u r i n t h e co n erio n p r o c e a n o t h e r a a n t a e i th e a ili t y t o r e a th e a ta a t a n y p ee u p t o 0 mh wh i c h a c co m m o a t e o th th e l o w i i tal h o t in t e r f ace a n t h e fa t e t e r i al r e ain t o r e u ce p e r f o r ma n c e e r aa t io n u e to i i t a l ac t i i ty a fat i c on t i n u ou cl o c k of a t l e a t 1 m h i re c o m m e n e to en u r e t h a t al l t h e i t a r e r e a u r i n t h e f i r t half o f t h e co n erio n p h a e i t i al o p o i le t o e i n t o r e a a ta a f t e r co n erio n a n co n t in ue t o r e a t h e la t i t a f t e r a n e w co n erio n ha e en ini t ia t e thi al lo w t h e u e o f a l o w er clo c k p e e li k e 1 mh f i nal l y in thi m o e o n l y th e ad7652 p r o ie a a iy-c h a i n f e a t ur e uin th e rd cs d in p i n f o r ca c ain m u l t i p le co n er t e r t o e t h er thi fe a t ur e i u ef u l fo r r e u cin co m p o n en t co un t a n wir i n co nn ec tio n wh en eir e a f o r in t a n ce in i ola t e m u l t ico n e r t er a p plica t io n an ea m ple o f t h e co n c a t ena t io n o f tw o e ice i h o w n in s i m u l t a n eo u a m p lin i p o i le y uin a co mm o n cn s t i n al i t h o u l e n o t e tha t th e rd cs d in i n put i l a tche on t h e opp o i te e e of s c l of t h e one u e to h if t o u t t h e a t a o n s d o u t th er efo r e t h e ms b o f t h e u p tr ea m co n e r t e r u t f o llo w th e l s b o f th e o w n tr ea m co n er t e r o n th e n e t scl c y c l e f i ur e 6 f i g u r e 36. t w o a d 7652s in a d a is y- chain conf ig ur at ion sclk sdout rdc/sdin bu s y bu s y data out ad7652 1 (do wnstream) busy out sclk ad7652 2 (upstream) rdc/sdin sdout sclk in cnvst in 02965-0-019 cnvst cs cnvst cs cs in rev. 0 page 23 of 28
ad7652 microprocessor interfacing th e ad7652 is ideal l y s u i t ed f o r tradi t io nal dc m e as ur em en t a p pl i c a t i o ns supp or t i ng a m i c r opro c e ss or , and f o r a c s i g n a l p r o c essin g a p plica t io n s in t e r f acin g t o a dig i t a l sig n a l p r o c ess o r . th e ad7652 is desig n ed t o in t e r f ace ei th er wi th a p a ral l e l 8-b i t o r 16-b i t wide in t e r f ace , o r wi th a g e n e ral-p u r p os e s e r i al p o r t o r i / o p o r t s on a m i c r o c on t r o l l e r . a v a r i e t y of e x te r n a l bu f f e r s c a n be us ed wi th th e ad7652 t o p r ev en t dig i tal n o is e f r o m co u p lin g in t o t h e ad c. th e fol l o w in g s e c t io n dis c uss e s t h e us e o f a n ad7652 wi th a n ads p -219x s p i eq ui p p ed ds p . spi interface (adsp-219x) f i gur e 3 7 f i g u r e 37. inter f acing t h e a d 7652 to an spi inter f ac e s h o w s a n in t e r f ace dia g ra m betw een th e ad7652 a n d th e s p i eq ui p p ed ads p -219x. t o acco mm o d a t e th e s l o w er s p eed o f th e ds p , th e ad7652 ac ts as a s l a v e device a n d da ta m u s t be r e ad a f t e r co n v ersio n . this m o de als o al lo ws th e da isy- cha i n fe a t ur e. th e co n v er t co mma n d ca n b e ini t ia te d in re sp ons e to an i n te r n a l t i me r i n te r r upt . the re a d i n g pro c e s s c a n b e ini t ia t e d in r e sp o n s e t o t h e en d-o f -co n v e rsio n sig n a l (b us y go in g lo w) usin g a n in t e r r u p t lin e o f t h e ds p . th e s e r i a l in t e r - face (s p i ) o n th e ads p -219x is co nf igur ed f o r mas t er m o de (ms t r) = 1, c l o c k p o la r i ty b i t (cpol) = 0, c l o c k phas e b i t (cp h a) = 1, a n d s p i i n t e r r u p t ena b le (tim o d ) = 00b y w r it i n g to t h e spi c o n t ro l re g i ste r ( s pic l t x ) . t o me e t a l l t i m i ng r e q u ir em en ts, t h e s p i clo c k s h o u ld b e limi t e d t o 17 mb ps, w h ich al lo ws i t t o r e ad a n ad c r e s u l t in les s tha n 1 s. w h en a hig h er s a m p lin g ra t e is desir e d , us e o f o n e o f t h e p a ral l e l in t e r f ace m o des is r e co mm en de d . ad7652* adsp-219x* ser/par pfx misox sckx pfx or tfsx bu s y sdout sclk cnvst ext/int cs rd invsclk dv d d * additional pins omitted for clarity spixsel (pfx) 02965-0-021 rev. 0 page 24 of 28
ad7652 application hints bipolar and wider input ranges i n s o m e a p plica t io n s , i t is desira b l e t o us e a b i p o la r o r wider a n alog in p u t ra n g e s u c h as 10 v , 5 v , o r 0 v t o 5 v . al th o u g h th e ad7652 has o n l y o n e uni p ola r ra n g e , sim p le m o dif i ca tio n s o f in p u t dr i v er cir c ui t r y a l lo w b i p o la r a n d wider in p u t r a n g es to b e u s e d w i t h out an y p e r f or m a nc e d e g r a d a t i o n . show s a co n n ecti o n d i a g ra m th a t allo w s th i s . c o m p o n e n t v a l u e s r e q u ir e d a n d r e su l t in g f u l l -s ca le ra n g es a r e sh o w n i n . f i g u re 3 8 f i gur e 3 8 f i g u r e 38. u s ing t h e a d 7652 in 16-bit bipolar and/or w i der input rang es t a b l e 8 ta ble 8. component va lues a nd input ra nges w h en desir e d , acc u ra t e ga in a n d o f fs et ca n be cali b r a t ed b y a c qu i r i n g a g r ou nd and volt age re fe re nc e u s i n g an an a l o g m u l t i p lexer (u2), as s h o w n i n . u1 analog input r2 r3 r4 100nf r1 u2 c ref in ingnd ref refgnd ad7652 02965-0-022 c f 15 ? th e ad7652 has v e r y g o o d imm u ni ty t o n o is e o n th e p o w e r su p p l i e s . h o we ve r , c a re shou l d st i l l b e t a k e n wi t h re g a rd to gr o u n d i n g l a y o u t . th e p r in t e d cir c ui t bo a r d tha t h o us es th e ad7652 s h o u ld be desig n e d s o t h e a n a l o g a n d dig i t a l s e c t io n s a r e s e p a r a te d a n d c o n f i n e d to c e r t ai n are a s of t h e b o ard. t h i s f a c i l i t a te s t h e u s e of g r o u n d pla n es t h a t ca n b e s e p a r a te d e a si ly . dig i t a l a n d a n a l o g g r ou nd pl ane s shou l d b e j o i n e d i n on ly one pl a c e, pre f e r ably un der n ea th th e ad7652, o r as c l os e as p o s s i b le t o th e ad7652. i f th e ad7652 is in a sys t em wh er e m u l t i p le devices r e q u ir e a n alog- t o- d i gi tal gr o u n d co n n ecti o n s, th e co n n ecti o n s h o u ld st i l l b e made a t one p o in t on ly , a st ar g r ou nd p o in t t h a t shou l d be es ta b l is h e d as c l os e as p o s s i b le t o th e ad7652. r u nnin g dig i t a l lin e s un der t h e de vice sh o u ld b e a v o i de d sin c e t h es e wi l l co u p le n o is e o n t o t h e die . th e a n alog g r o u n d pla n e s h o u ld be al lo w e d t o r u n un der th e ad7652 t o a v o i d n o is e co u p lin g . f a s t swi t c h in g sig n als lik e cnv s t or cl o c k s shou l d b e shielde d wi t h dig i t a l g r o u n d to a v o i d r a dia t in g n o is e to o t h e r s e c t i o ns of t h e b o ard, and shou l d ne ve r r u n ne ar an a l o g s i g n a l p a th s. cr os s o v e r o f dig i tal a n d a n alog sig n als s h o u ld be a v o i de d . t r aces o n dif f er en t b u t clos e la yers o f t h e b o a r d s h o u ld r u n a t r i g h t a n g l es t o eac h o t h e r . this wil l r e d u ce th e ef f e c t o f cr os s t al k th r o ugh th e boa r d . th e p o w e r s u p p l y lin e s t o th e ad7652 s h o u ld us e as la rg e a t r ace as p o s s i b le t o p r o v ide lo w im p e da n c e p a t h s a n d r e d u ce t h e ef f e c t o f g l i t c h es o n th e p o w e r s u p p l y lin e s. g o o d deco u p lin g is als o im p o r t a n t t o lo w e r t h e s u p p l y s im p e da n c e p r es en t e d t o t h e ad7652 a n d t o r e d u ce th e ma g n i t ude o f th e s u p p l y s p ik es. deco u p lin g cera mic ca p a ci t o rs, typ i cal l y 100 nf , s h o u ld be p l a c ed o n ea c h po w e r s u p p l y p i n a v d d , d v d d , a n d o v dd c l o s e to , and i d e a l l y r i g h t up ag ai nst t h e s e pi ns and t h e i r c o r r e s p o nd i n g g r ou nd pi ns . a d d i t i on a l ly , l o w e s r 1 0 f c a p a c i tors shou l d b e l o c a te d ne ar t h e a d c to f u r t he r re d u c e lo w f r e q uen c y r i p p le . th e d v d d s u p p l y o f th e ad7652 ca n be a s e p a ra t e s u p p l y o r ca n co m e f r o m th e a n alog s u p p l y a v d d o r th e d i gi tal i n t e rfa c e su p p ly o v dd . w h e n t h e s y ste m dig i t a l su p p ly is nois y or w h e n fas t swi t c h in g dig i tal sig n als a r e p r es en t, if n o s e p a ra t e s u p p l y is a v a i la b l e , th e us er s h o u ld co nn ec t d v d d t o a v d d thr o ug h a n r c f i l t er (s e e f ) a n d t h e sys t em s u p p l y t o o v d d a n d th e r e m a i n i n g d i gi tal ci r c ui tr y . w h e n d v d d i s po w e r e d f r o m th e sys t em s u p p l y , i t is us ef u l t o in s e r t a bead t o f u r t h e r r e d u ce hig h f r e q uen c y sp i k es. i gur e 2 2 th e ad7652 has f i v e dif f er en t g r o u n d p i n s : in gnd , refgnd , a g nd , d g nd , a n d o g nd . in gnd is us e d to s e n s e t h e a n a l o g in p u t sig n al . refgnd s e n s es t h e r e fer e n c e v o l t a g e a n d , b e ca us e i t ca r r i es p u ls e d c u r r en ts, s h o u ld be a lo w im p e da n c e r e t u r n t o t h e r e fer e n c e . a g nd is t h e g r o u n d t o w h ich m o st in t e r n a l ad c a n alog si gn als a r e r e f e r e n c ed ; i t m u s t be co n n ect e d w i th th e l e a s t re s i st anc e to t h e an a l o g g r ou nd pl ane. d g n d m u st b e t i e d to t h e an a l o g or d i g i t a l g r ou nd pl ane d e p e nd i n g on t h e co nf igur a t io n. o g nd is co nn e c te d to t h e dig i t a l sy stem g r ou nd. evaluating the ad7652s performance a r e co mm en ded la yo u t f o r th e ad7652 is o u tlin ed in th e e v al -ad7652 eval ua tio n bo a r d f o r th e ad7652. th e e v a l u a t i on b o ard p a ck age i n clu d e s a f u l l y a s s e m b l e d and te ste d e v a l ua t i o n b o a r d , do c u m e n t a t io n, a n d s o f t wa r e fo r co n t r o l l in g t h e b o a r d f r o m a pc via t h e ev a l -c ontrol br d 2 . rev. 0 page 25 of 28
ad7652 preliminary technical data outline dimensions top view (pins down ) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc s q seating plane 1.60 ma x 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.10 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 10 6 2 0.15 0.05 compliant to jedec standards ms-026bbc f i g u r e 39. 48-l e ad q u ad f l at pack (l qfp ) [st - 48] d i mens ions s h o wn in millimeters pin 1 indicator top view 6.75 bs c s q 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane paddle connected to agnd. this connection is not required to meet the electrical performances 0. 25 m i n 0. 2 0 r e f compliant to jedec standards mo-220-vkkd-2 f i g u r e 40. 48-l e ad f r ame chip s c ale p a ck age (lfcsp ) [cp - 48] d i mens ions s h o wn in millimeters ordering guide model temperature range package description package option ad7652ast C40c to 85c quad flatpack (lqfp) st-48 ad7652astrl C40c to 85c qu ad flatpack (lqfp) st-48 AD7652ACP C40c to 85c lead frame chip scale (lfcsp) cp-48 AD7652ACPrl C40c to 85c lead frame chip scale (lfcsp) cp-48 eval-ad7652cb 1 e v a l u a t i o n b o a r d eval-control brd2 2 c o n t r o l l e r b o a r d 1 th i s boa r d ca n be used a s a st a n da lon e eva l ua t i on boa r d or i n con j u n c t i on wi t h t h e eval- c on tr ol br d 2 for eva l ua t i on /dem on st ra t i on purposes. 2 th i s boa r d a llows a pc t o con t r ol a n d com m u n i ca t e wi t h a ll an a l og d e vi ces eva l ua t i on boa r ds en di n g i n t h e cb desi gn a t ors. rev. 0 page 26 of 28
ad7652 notes rev. 0 | page 27 of 28
ad7652 notes 200 analo deice inc all ri ht reere traemark an reitere traemark are the prop erty of their repectie owner c0265000 rev. 0 | page 28 of 28

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